1. Technical Field
The invention relates to nanotechnology. In particular, the invention relates to a device that has nanowires incorporated between coaxial electrodes and an array of such devices.
2. Description of Related Art
Historically, high performance semiconductor devices, especially those with p-n junctions, comprise single crystals of one or more semiconductor materials. Among other things, using such single crystalline materials for semiconductor devices essentially eliminates the scattering of charged carriers (e.g., holes and electrons) at grain boundaries that exist in non-single crystalline semiconductor materials such as polycrystalline semiconductor materials. Such scattering adversely reduces the drift mobility and the diffusion of charged carriers, and leads to a degraded performance (e.g., increased resistance) of devices, such as transistors and solar cells. Even when different semiconductor materials were employed together in a single device, such as in a heterostructure or heterojunction device, single crystalline semiconductor materials are generally chosen based on their respective lattice structures to insure that the structure realized is an essentially single crystalline structure as a whole. Similarly, nanostructures including, but not limited to, nanowires and nanodots are typically nucleated and grown from single crystalline substrates, in part to capitalize on the uniform nature of the lattice of such substrates that provides required crystallographic information for the nanostructures to be grown as single crystals.
In addition to single crystalline semiconductors, amorphous and other essentially non-single crystalline semiconductor materials also have been attracting attention, in particular, in solar cell and silicon photonics applications. While having the disadvantages associated with multiple grain boundaries, such non-single crystalline semiconductor materials can be considerably cheaper to manufacture than their single crystalline counterparts. In many applications, the lower cost of producing the semiconductor device from non-single crystalline materials may outweigh any loss of performance that may or may not result. Furthermore, using non-single crystalline semiconductor materials for heterostructures can increase the possible combinations of materials that can be used since lattice mismatch is less of a concern with non-single crystalline semiconductors.
For example, heavily doped polycrystalline silicon (Si) is commonly used instead of or in addition to metal for conductor traces in integrated circuits where the heavy doping essentially overcomes the increased resistivity associated with carrier scattering from the multiple grain boundaries. Similarly, polycrystalline Si is commonly used in solar cells where its relatively lower cost outweighs the decrease in performance associated with the nature of the polycrystalline material. Amorphous semiconductor material is similarly finding applications in solar cells and in thin film transistors (TFTs) for various optical display applications where cost generally dominates over concerns about performance.
Unfortunately, the ability to effectively combine non-single crystalline semiconductor materials with single crystalline semiconductor materials to realize semiconductor junction-based devices and heterostructure or heterojunction devices has generally met with little success. In part, this is due to the disruptive effects that joining a single crystalline layer to a non-single crystalline layer has on the physical properties of the single crystalline layer. As such, devices that employ nanostructures as active elements typically use single crystalline materials to interface to single crystalline nanostructures. For example, solar cell devices that incorporate nanowires employ single crystalline materials to form semiconductor junctions.